 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 1. general description the PCF85063TP is a cmos 1 real-time clock (rtc) and calendar optimized for low power consumption. an offset register allows fine-tuning of the clock. all addresses and data are transferred serially via the two-line bidirectional i 2 c-bus. maximum bus speed is 400 kbit/s. the register address is incremen ted automatically after each written or read data byte. 2. features and benefits ? provides year, month, day, weekday, hours, minutes, and seconds based on a 32.768 khz quartz crystal ? clock operating voltage: 0.9 v to 5.5 v ? low current: typical 0.22 ? aat v dd = 3.3 v and t amb =25 ? c ? 400 khz two-line i 2 c-bus interface (at v dd = 1.8 v to 5.5 v) ? programmable clock output for periphe ral devices (32.768 khz, 16.384 khz, 8.192 khz, 4.096 khz, 2.048 khz, 1.024 khz, and 1 hz) ? selectable integrated oscilla tor load capacitors for c l =7pf or c l = 12.5 pf ? minute and half minute interrupt ? internal power-on reset (por) ? programmable offset register for frequency adjustment 3. applications ? digital still camera ? digital video camera ? printers ? copy machines ? mobile equipment ? battery powered devices PCF85063TP tiny real-time clock/calendar rev. 2 ? 15 april 2013 product data sheet 1. the definition of the abbreviations and acronyms used in this data sheet can be found in section 19 .
PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 2 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 4. ordering information 4.1 ordering options 5. marking 6. block diagram table 1. ordering information type number package name description version PCF85063TP hwson8 plastic thermal enhanced very very thin small outline package; no leads; 8 terminals; body 2 ? 3 ? 0.75 mm sot1069-2 table 2. ordering options product type number ic revision sales item (12nc) delivery form PCF85063TP/1 1 935297365118 tape and reel, 13 inch table 3. marking codes product type number marking code PCF85063TP/1 063 fig 1. block diagram of PCF85063TP PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 3 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 7. pinning information 7.1 pinning 7.2 pin description [1] the die paddle (exposed pad) is connected to v ss and should be electrically isolated. for mechanical details, see figure 27 . fig 2. pin configuration for hwson8 (PCF85063TP) !"#$% "#& '$ $ % $#()$ # *)+" , - . / 0 1 table 4. pin description symbol pin type description osci 1 input oscillator input osco 2 output oscillator output int 3 output interrupt output (open-drain) vss 4 [1] supply ground supply voltage sda 5 input/output serial data line scl 6 input serial clock input clkout 7 output clock output (push-pull) vdd 8 supply supply voltage PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 4 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 8. functional description the PCF85063TP contains 11 8-bit registers with an auto-incrementing register address, an on-chip 32.768 khz oscillator with integr ated capacitors, a freq uency divider which provides the source clock for the real-time clock (rtc) and calender, and an i 2 c-bus interface with a maximum data rate of 400 kbit/s. the built-in address register will increment automatically after ea ch read or write of a data byte up to the register 0ah. after register 0ah, the auto -incrementing will wrap around to address 00h (see figure 3 ). all 11 registers (see ta b l e 5 ) are designed as addressable 8-bit parallel registers although not all bits are implemented. the first two registers (memory address 00h and 01h) are used as control and status register. the regi ster at address 02h is an offset register allowing the fine-tuning of the clock; and at 03h is a free ram byte. the addresses 04h through 0ah are used as counters for the cloc k function (seconds up to years counters). the seconds, minutes, hours, days, months, and years registers are all coded in binary coded decimal (bcd) format. when one of the rtc registers is written or read, the contents of all time counters are frozen. therefore, faulty writing or reading of the clock and calendar during a carry condition is prevented. fig 3. handling address registers $&& (( 2"( 334 $5 *"#6 ! # , $)$ *5#& 3%4 34 34 777 3.4 384 3 4 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 5 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 8.1 registers organization table 5. registers overview bit positions labeled as - are not implemented. after reset, all registers are set according to table 8 on page 9 . address register name bit reference 7 6 5 4 3 2 1 0 control and status registers 00h control_1 ext_test - stop sr - cie 12_24 cap_sel section 8.2.1 01h control_2 - - mi hmi tf cof[2:0] section 8.2.2 02h offset mode offset[6:0] section 8.2.3 03h ram_byte b[7:0] section 8.2.4 time and date registers 04h seconds os seconds (0 to 59) section 8.3.1 05h minutes - minutes (0 to 59) section 8.3.2 06h hours - - ampm hours (1 to 12) in 12 hour mode section 8.3.3 hours (0 to 23) in 24 hour mode 07h days - - days (1 to 31) section 8.3.4 08h weekdays - - - - - weekdays (0 to 6) section 8.3.5 09h months - - - months (1 to 12) section 8.3.6 0ah years years (0 to 99) section 8.3.7 PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 6 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 8.2 control registers 8.2.1 register control_1 [1] default value. [2] for a software reset, 01011000 (58h) must be sent to register control_1 (see section 8.2.1.3 ). 8.2.1.1 ext_test: external clock test mode a test mode is available which allows for on-boar d testing. in this mode, it is possible to set up test conditions and control the operation of the rtc. the test mode is entered by setting bit ext_test in register control_1. then pin clkout becomes an input. the test mode replaces the internal clock signal with the signal applied to pin clkout. the signal applied to pin clkout should have a minimum pulse width of 300 ns and a maximum period of 1000 ns. the internal cl ock, now sourced from clkout, is divided down to 1 hz by a 2 6 divide chain called a prescaler. the prescaler can be set into a known state by using bit stop. when bit stop is set, the prescaler is reset to 0. (stop must be cleared before the prescaler can operate again.) table 6. control_1 - control and status re gister 1 (address 00h) bit description bit symbol value description reference 7 ext_test external clock test mode section 8.2.1.1 0 [1] normal mode 1 external clock test mode 6 - 0 unused - 5stop stop bit section 8.2.1.2 0 [1] rtc clock runs 1 rtc clock is stopped; all rtc divider chain flip-flops are asynchronously set logic 0 4sr software reset section 8.2.1.3 0 [1] no software reset 1 initiate software reset [2] ; this bit always returns a 0 when read 3 - 0 unused - 2cie correction interrupt enable section 8.2.3 0 [1] no correction interrupt generated 1 interrupt pulses are generated at every correction cycle 1 12_24 12 or 24 hour mode section 8.3.3 0 [1] 24 hour mode is selected 1 12 hour mode is selected 0 cap_sel internal oscillator capacitor selection for quartz crystals with a corresponding load capacitance - 0 [1] 7 pf 1 12.5 pf PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 7 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar from a stop condition, the fi rst 1 second increment will take place after 32 positive edges on pin clkout. thereafter, every 64 pos itive edges cause a 1 second increment. remark: entry into test mode is not synchroni zed to the internal 64 hz clock. when entering the test mode, no assumption as to the state of the prescaler can be made. operation example: 1. set ext_test test mode (regis ter control_1, bit ext_test = 1) 2. set stop (register control_1, bit stop = 1) 3. clear stop (register control_1, bit stop = 0) 4. set time registers to desired value 5. apply 32 clock pulses to pin clkout 6. read time registers to see the first change 7. apply 64 clock pulses to pin clkout 8. read time registers to see the second change repeat 7 and 8 for additional increments. 8.2.1.2 stop: stop bit function the function of the stop bit (see figure 4 ) is to allow for accurate starting of the time circuits. the stop bit function causes the upper part of the prescaler (f 2 to f 14 ) to be held in reset and thus no 1 hz ticks are generated. it also stops the output of clock frequencies lower than 8 khz on pin clkout. the time circuits can then be set and do not increment until the stop bit is released (see figure 5 and ta b l e 7 ). fig 4. stop bit functional diagram ( "#2 4 9$2 3 /0. %0.- .%8 -380 % "6 % % %- PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 8 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar [1] f 0 is clocked at 32.768 khz. the lower two stages of the prescaler (f 0 and f 1 ) are not reset. and because the i 2 c-bus is asynchronous to the crystal oscillator, the accuracy of restarting the time circuits is between zero and one 8.192 khz cycle (see figure 5 ). the first increment of the time circuits is between 0.507813 s and 0.507935 s after stop bit is released. the uncertainty is caused by the prescaler bits f 0 and f 1 not being reset (see table 7 ) and the unknown state of the 32 khz clock. table 7. first increment of time circuits after stop bit release bit prescaler bits [1] 1hz tick time comment stop f 0 f 1 -f 2 to f 14 hh:mm:ss clock is running normally 0 01-0 0001 1101 0100 12:45:12 prescaler counting normally stop bit is activated by user. f 0 f 1 are not reset and values cannot be predicted externally 1 xx-0 0000 0000 0000 12:45:12 prescaler is reset; time circuits are frozen new time is set by user 1 xx-0 0000 0000 0000 08:00:00 prescaler is reset; time circuits are frozen stop bit is released by user 0 xx-0 0000 0000 0000 08:00:00 prescaler is now running xx-1 0000 0000 0000 08:00:00 - xx-0 1000 0000 0000 08:00:00 - xx-1 1000 0000 0000 08:00:00 - : :: 11-1 1111 1111 1110 08:00:00 - 00-0 0000 0000 0001 08:00:01 0 to 1 transition of f 14 increments the time circuits 10-0 0000 0000 0001 08:00:01 - : :: 11-1 1111 1111 1111 08:00:01 - 00-0 0000 0000 0000 08:00:01 - 10-0 0000 0000 0000 08:00:01 - : :: 11-1 1111 1111 1110 08:00:01 - 00-0 0000 0000 0001 08:00:02 0 to 1 transition of f 14 increments the time circuits %73 33333( 37 13/.% * 371 3/81( fig 5. stop bit release timing 3:( *%:( .%8 ( *) $( & PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 9 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 8.2.1.3 software reset a reset is automatically generated at power-o n. a reset can also be initiated with the software reset command. software reset command means setting bits 6, 4, and 3 in register control_1 (00h) logic 1 and all other bits logic 0 by sending the bit sequence 01011000 (58h), see figure 6 . in reset state all regist ers are set according to ta b l e 8 and the address pointer returns to address 00h. the PCF85063TP resets to: time ? 00:00:00 date ? 20000101 weekday ? saturday fig 6. software reset command ( %3%333% 3 33333333 3%3%% 333 ; ($+ $&& (( $&& ((334 (*9 ,$ ( 1.4 ; "# #$ ( ("2#$ table 8. register reset values address register name bit 7 6 5 4 3 2 1 0 00h control_1 00000000 01h control_2 00000000 02h offset 00000000 03h ram_byte 00000000 04h seconds 10000000 05h minutes 00000000 06h hours 00000000 07h days 00000001 08h weekdays 00000110 09h months 00000001 0ah years 00000000 PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 10 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 8.2.2 register control_2 [1] default value. 8.2.2.1 mi and hmi: minute and half minute interrupt the minute interrupt (bit mi) and half minute in terrupt (bit hmi) are pre-defined timers for generating interrupt pulses on pin int ; see figure 7 . the timers are running in sync with the seconds counter (see table 19 on page 16 ). when starting mi, the first in terrupt will be generated after 1 second to 59 seconds. when starting hmi, the first in terrupt will be generated after 1 second to 29 seconds. subsequent periods do not have such a delay. the timers can be enabled independently from one another. however, a minute interrupt enabled on top of a half minute interrupt is not distinguishable. table 9. control_2 - control and status re gister 2 (address 01h) bit description bit symbol value description 7 to 6 - 00 unused 5mi minute interrupt 0 [1] disabled 1 enabled 4hmi half minute interrupt 0 [1] disabled 1 enabled 3tf timer flag 0 [1] no timer interrupt generated 1 flag set when timer interrupt generated 2 to 0 cof[2:0] see ta b l e 11 clkout control in this example, the tf flag is not cleared after an interrupt. fig 7. int example for mi table 10. effect of bits mi and hmi on int generation minute interrupt (bit mi) half minute inte rrupt (bit hmi) result 0 0 no interrupt generated 1 0 an interrupt every minute 0 1 an interrupt every 30 s 1 1 an interrupt every 30 s 1. ( 6*#&(6*5# !"#5 (6*5# ,4 # #$< & ,4 # #$< & 18 18 %% 33 3%33 % PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 11 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar the duration of the timer is affected by the register offset (see section 8.2.3 ). only when offset[6:0] has the value 00h the periods are consistent. 8.2.2.2 tf: timer flag the timer flag (bit tf) is set logic 1 on the first trigger of mi or hmi and remains set until it is cleared by command. 8.2.2.3 cof[2:0]: clock output frequency a programmable square wave is available at pin clkout. operation is controlled by the cof[2:0] bits in the register control_2. fr equencies of 32.768 khz (default) down to 1 hz can be generated for use as a system clock, microcontroller clock, input to a charge pump, or for calibration of the oscillator. pin clkout is a push-pull output and enabled at power-on. clkout can be disabled by setting cof[2:0] to 111. when disabled, the clkout is low. the duty cycle of the selected clock is not c ontrolled but due to the nature of the clock generation, all clock frequencies except 32.768 khz have a duty cycle of 50 : 50. the stop bit function can also affect the clkout signal, depending on the selected frequency. when the stop bit is set logic 1, the clkout pin generates a continuous low for those frequencies that can be stopped. for more details of the stop bit function, see section 8.2.1.2 . [1] duty cycle definition: % high-level time : % low-level time. [2] default value. [3] 1 hz clock pulses are affected by offset correction pulses. 8.2.3 register offset the PCF85063TP incorporates an offset register (address 02h) which can be used to implement several functions, such as: ? accuracy tuning ? aging adjustment ? temperature compensation table 11. clkout frequency selection cof[2:0] clkout frequency (hz) typical duty cycle [1] effect of stop bit 000 [2] 32768 60 : 40 to 40 : 60 no effect 001 16384 50 : 50 no effect 010 8192 50 : 50 no effect 011 4096 50 : 50 clkout = low 100 2048 50 : 50 clkout = low 101 1024 50 : 50 clkout = low 110 1 [3] 50 : 50 clkout = low 111 clkout = low - - PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 12 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar [1] default value. for mode = 0, each lsb introduces an offs et of 4.34 ppm. for mode = 1, each lsb introduces an offset of 4.069 ppm. the valu es of 4.34 ppm and 4.069 ppm are based on a nominal 32.768 khz clock. the offset value is coded in two?s complement giving a range of +63 lsb to ? 64 lsb. [1] default value. the correction is made by adding or subtra cting clock correction pulses, thereby changing the period of a single second but not by changing the oscillator frequency. it is possible to monitor when correction pulses are applied. to enable correction interrupt generation, bit cie (register control_1) has to be set logic 1. at every correction cycle a pulse is generated on pin int . the pulse width depends on the correction mode. if multiple correction pulses are applied, an interrupt pulse is generated for each correction pulse applied. table 12. offset - offset register (address 02h) bit description bit symbol value description 7mode offset mode 0 [1] normal mode: offset is made once every two hours 1 course mode: offset is made every 4 minutes 6 to 0 offset[6:0] see ta b l e 1 3 offset value table 13. offset values offset[6:0] offset value in decimal offset value in ppm normal mode mode = 0 fast mode mode = 1 0111111 +63 +273.420 +256.347 0111110 +62 +269.080 +252.278 :: : : 0000010 +2 +8.680 +8.138 0000001 +1 +4.340 +4.069 0000000 [1] 00 [1] 0 [1] 1111111 ? 1 ? 4.340 ? 4.069 1111110 ? 2 ? 8.680 ? 8.138 :: : : 1000001 ? 63 ? 273.420 ? 256.347 1000000 ? 64 ? 277.760 ? 260.416 PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 13 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 8.2.3.1 correction when mode = 0 the correction is triggered once every two ho urs and then correction pulses are applied once per minute until the programmed correction values have been implemented. [1] the correction pulses on pin int are 1 64 s wide. in mode = 0, any timer or clock output using a frequency below 64 hz is affected by the clock correction (see ta b l e 1 5 ). table 14. correction pulses for mode = 0 correction value update every n th hour minute correction pulses on int per minute [1] +1 or ? 12 00 1 +2 or ? 2 2 00 and 01 1 +3 or ? 3 2 00, 01, and 02 1 :::: +59 or ? 59 2 00 to 58 1 +60 or ? 60 2 00 to 59 1 +61 or ? 61 2 00 to 59 1 2nd and next hour 00 1 +62 or ? 62 2 00 to 59 1 2nd and next hour 00 and 01 1 +63 or ? 63 02 00 to 59 1 2nd and next hour 00, 01, and 02 1 ? 64 02 00 to 59 1 2nd and next hour 00, 01, 02, and 03 1 table 15. effect of correction pu lses on frequencies for mode = 0 frequency (hz) effect of correction clkout 32768 no effect 16384 no effect 8192 no effect 4096 no effect 2048 no effect 1024 no effect 1affected timer source clock 4096 no effect 64 no effect 1affected 1 60 affected PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 14 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 8.2.3.2 correction when mode = 1 the correction is triggered once every four minutes and then correction pulses are applied once per second up to a maximum of 60 pulse s. when correction values greater than 60 pulses are used, additional correction pulses are made in the 59 th second. clock correction is made more frequently in mode = 1; however, this can result in higher power consumption. [1] the correction pulses on pin int are 1 1024 s wide. for multiple pulses, they are repeated at an interval of 1 512 s. in mode = 1, any timer source clock using a frequency below 1.024 khz is also affected by the clock correction (see ta b l e 1 7 ). table 16. correction pulses for mode = 1 correction value update every n th minute second correction pulses on int per second [1] +1 or ? 12 00 1 +2 or ? 2 2 00 and 01 1 +3 or ? 3 2 00, 01, and 02 1 :::: +59 or ? 59 2 00 to 58 1 +60 or ? 60 2 00 to 59 1 +61 or ? 61 2 00 to 58 1 25 92 +62 or ? 62 2 00 to 58 1 25 93 +63 or ? 63 2 00 to 58 1 25 94 ? 64 2 00 to 58 1 25 95 table 17. effect of correction pu lses on frequencies for mode = 1 frequency (hz) effect of correction clkout 32768 no effect 16384 no effect 8192 no effect 4096 no effect 2048 no effect 1024 no effect 1affected timer source clock 4096 no effect 64 affected 1affected 1 60 affected PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 15 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 8.2.3.3 offset calibration workflow the calibration offset has to be calculated based on the time. figure 8 shows the workflow how the offset register values can be calculated: fig 8. offset calibratio n calculation workflow $(5 4 9 =5 #6>*#)"# ? 9 ! $( *#+ * "! ? ! $( @%;9 ! $( $65$ 4 &"99 #6 * 4 "& $ ) "*&*9%;/0.733? ! $( @%;/0. ! $( $65$ 4 ))!& +"$ "*#6*!)$ & * 4 ! $(5 &+$5 ? ))! @%333333a ! $( ; ! $( $65$ 4 *99( 2"( +$5 ? *& @3b*,)*, c? 99( +$5 @ ))! ;-7- *& @%b9$( 6* 6 "*#c 99( +$5 @ ))! ;-7308 ($!) 6$65$ "*#? /0.7-. 371%/%%:( 37333--/:( %-70-.))! 7/1 6* 6 "*#)5( ( $ # & & 7033 -6* 6 "*#)5( ( $ # & & PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 16 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 8.2.4 register ram_byte the PCF85063TP provides a free ram byte, which can be used for any purpose, for example, status byte of the system. [1] default value. 8.3 time and date registers most of the registers are coded in the bcd format to simplify application use. 8.3.1 register seconds [1] default value. with the offset calibration an accuracy of ? 2 ppm (0.5 ? offset per lsb) can be reached (see table 13 ). ? 1 ppm corresponds to a time deviation of 0.0864 seconds per day. (1) 3 correction pulses in mode = 0 correspond to ? 13.02 ppm. (2) 4 correction pulses in mode = 1 correspond to ? 16.276 ppm. (3) reachable accuracy zone. fig 9. result of offset calibration 3 - 0 . %3 % %- %0 0 - bc bc b%c ! $(5 &;6$65$ & & +"$ "*#%-70-.))! & +"$ "*#$9 6* 6 "*#"# @3 d%70.))! & +"$ "*#$9 6* 6 "*#"# @% %70.))! table 18. ram_byte - 8-bit ram regist er (address 03h) bit description bit symbol value description 7 to 0 b[7:0] 00000000 [1] to 11111111 ram content table 19. seconds - seconds register (address 04h) bit description bit symbol value place value description 7os oscillator stop 0 - clock integrity is guaranteed 1 [1] - clock integrity is not guaranteed; oscillator has stopped or has been interrupted 6to4 seconds 0 [1] to 5 ten?s place actual seconds coded in bcd format, see table 20 3 to 0 0 [1] to 9 unit place PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 17 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar [1] default value. 8.3.1.1 os: oscillator stop when the oscillator of the PCF85063TP is stopped , the os flag is se t. the oscillator can be stopped, for example, by connecting one of the oscilla tor pins osci or osco to ground. the oscillator is cons idered to be stopped during th e time between power-on and stable crystal resonance. this time can be in the range of 200 ms to 2 s depending on crystal type, temperature, and supply voltage. the flag remains set until cleared by command (see figure 10 ). if the flag cannot be cleared, then the oscillator is not running. this method can be used to monitor the oscillator and to determine if the supply volt age has reduced to the point where oscillation fails. table 20. seconds coded in bcd format seconds value in decimal upper-digit (ten?s place) digit (unit place) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 00 [1] 0000000 01 0000001 02 0000010 : ::::::: 09 0001001 10 0010000 : ::::::: 58 1011000 59 1011001 fig 10. os flag @%$#&9$26$##* < 6 $ & *(6"$ "*# *(6"$ "*##*,( $< 9$26 $ & <>(*9 ,$ 9$2( ,4 # *(6"$ "*#( *)( 9$2 @%$#&9$26$#< 6 $ & PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 18 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 8.3.2 register minutes [1] default value. 8.3.3 register hours [1] hour mode is set by the 12_24 bit in register control_1. [2] default value. 8.3.4 register days [1] if the year counter contains a value, which is exactly divisible by 4 (including the year 00), the PCF85063TP compensates for leap years by adding a 29th day to february. [2] default value. [3] default value is 1. 8.3.5 register weekdays table 21. minutes - minutes register (address 05h) bit description bit symbol value place value description 7 - 0 - unused 6to4 minutes 0 [1] to 5 ten?s place actual minutes coded in bcd format 3 to 0 0 [1] to 9 unit place table 22. hours - hours register (address 06h) bit description bit symbol value place value description 7 to 6 - 00 - unused 12 hour mode [1] 5ampm am/pm indicator 0 [2] -a m 1- p m 4 hours 0 [2] to 1 ten?s place actual hours in 12 hour mode coded in bcd format 3to0 0 [2] to 9 unit place 24 hour mode [1] 5 to 4 hours 0 [2] to 2 ten?s place actual hours in 24 hour mode coded in bcd format 3to0 0 [2] to 9 unit place table 23. days - days register (address 07h) bit description bit symbol value place value description 7 to 6 - 00 - unused 5to4 days [1] 0 [2] to 3 ten?s place actual day coded in bcd format 3to0 0 [3] to 9 unit place table 24. weekdays - weekdays register (address 08h) bit description bit symbol value description 7 to 3 - 00000 unused 2to0 weekdays 0to6 actual weekday values, see ta b l e 2 5 PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 19 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar [1] definition may be reassigned by the user. [2] default value. 8.3.6 register months [1] default value. table 25. weekday assignments day [1] bit 2 1 0 sunday 0 0 0 monday 0 0 1 tuesday 0 1 0 wednesday 0 1 1 thursday 1 0 0 friday 1 0 1 saturday [2] 110 table 26. months - months register (address 09h) bit description bit symbol value place value description 7 to 5 - 000 - unused 4 months 0 to 1 ten?s place actual month coded in bcd format, see table 27 3 to 0 0 to 9 unit place table 27. month assignments in bcd format month upper-digit (ten?s place) digit (unit place) bit 4 bit 3 bit 2 bit 1 bit 0 january [1] 00001 february 0 0 0 1 0 march 0 0 0 1 1 april00100 may00101 june00110 july00111 august01000 september 0 1 0 0 1 october10000 november10001 december10010 PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 20 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 8.3.7 register years [1] default value. 8.4 setting and reading the time figure 11 shows the data flow and data dependencies starting from the 1 hz clock tick. during read/write operations, the time counting circuits (memory locations 04h through 0ah) are blocked. the blocking prevents ? faulty reading of the clock and calendar during a carry condition ? incrementing the time regist ers during the read cycle after this read/write access is completed, the time circuit is released again and any pending request to increment the time counte rs that occurred during the read/write access is serviced. a maximum of 1 request can be stored; therefore, all accesses must be completed within 1 second (see figure 12 ). table 28. years - years register (0ah) bit description bit symbol value place value description 7 to 4 years 0 [1] to 9 ten?s place actual year coded in bcd format 3to0 0 [1] to 9 unit place fig 11. data flow for the time function % "6 %e-4*5 !*& PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 21 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar because of this method, it is very important to make a read or write access in one go, that is, setting or reading seconds through to years should be made in one single access. failing to comply with this method could result in th e time becoming corrupted. as an example, if the time (seconds through to hours) is set in one access and then in a second access the date is set, it is possible that the time will increment between the two accesses. a similar problem exists when reading. a roll-over may occur between reads thus giving the minutes from one moment and the hours from the next. recommended method for reading the time: 1. send a start condition and the slave address (see table 29 on page 24 ) for write (a2h) 2. set the address pointer to 4 (seconds) by sending 04h 3. send a restart condition or stop followed by start 4. send the slave address for read (a3h) 5. read seconds 6. read minutes 7. read hours 8. read days 9. read weekdays 10. read months 11. read years 12. send a stop condition fig 12. access time for read/write operations f%( PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 22 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 9. characteristics of the i 2 c-bus interface the i 2 c-bus is for bidirectional, two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up resistor. data transfer may be initiated only when the bus is not busy. 9.1 bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock puls e, as changes in the data line at this time are interpreted as a control signal (see figure 13 ). 9.2 start and stop conditions both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is high is defined as the start condition - s. a low-to-high transition of the data line while the clock is high is defined as the stop condition - p (see figure 14 ). 9.3 system configuration a device generating a message is a transm itter; a device receiving a message is a receiver. the device that controls the message is the master; and the devices which are controlled by the master are the slaves (see figure 15 ). fig 13. bit transfer mbc621 data line stable; data valid change of data allowed sda scl fig 14. definition of start and stop conditions mbc622 sda scl p stop condition sda scl s start condition PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 23 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 9.4 acknowledge the number of data bytes transferred between the start and stop conditions from transmitter to receiver is un limited. each byte of 8 bits is followed by an acknowledge cycle. ? a slave receiver, which is addressed, must generate an acknowledge after the reception of each byte ? also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter ? the device that acknowledges must pull-down the sda line during the acknowledge clock pulse, so that the sda line is st able low during the high period of the acknowledge related clock pulse (set-up and hold times must be considered) ? a master receiver must signal an end of da ta to the transmitter by not generating an acknowledge on the last byte that has been cl ocked out of the slave. in this event, the transmitter must leave the data line high to enable the master to generate a stop condition acknowledgement on the i 2 c-bus is shown in figure 16 . fig 15. system configuration mga807 sda scl master transmitter/ receiver master transmitter slave transmitter/ receiver slave receiver master transmitter/ receiver fig 16. acknowledgement on the i 2 c-bus mbc602 s start condition 9 8 2 1 clock pulse for acknowledgement not acknowledge acknowledge data output by transmitter data output by receiver scl from master PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 24 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 9.5 i 2 c-bus protocol 9.5.1 addressing one i 2 c-bus slave address (1010001) is rese rved for the PCF85063TP. the entire i 2 c-bus slave address byte is shown in ta b l e 2 9 . after a start condition, the i 2 c slave address has to be sent to the PCF85063TP device. the r/w bit defines the direction of the following single or multiple byte data transfer (r/w = 0 for writing, r/w = 1 for reading). for the format and the timing of the start condition (s), the stop condition (p) and the acknowledge bit (a) refer to the i 2 c-bus characteristics (see ref. 12 ? um10204 ? ). in the write mode, a data transfer is terminated by sending either the stop condition or the start condition of the next data transfer. 9.5.2 clock and calendar read or write cycles the i 2 c-bus configuration for the different pc f85063tp read and write cycles is shown in figure 17 and figure 18 . the register address is a 4-bit value that defines which register will be accessed next . the upper 4 bits of the r egister address are not used. table 29. i 2 c slave address byte slave address bit 7 6 5 4 3 2 1 0 msb lsb 1010001r/w fig 17. master transmits to slave receiver (write mode) % 3%333%3 ; $6#*, &2 9 *!.130 $6#*, &2 9 *!.130 $6#*, &2 9 *!.130 ($+ $&& (( , " <" 2"( $&& (( 334 *3 4 3 *# &$ $<> ( ; PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 25 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar for multimaster configurations and to fasten the communi cation, the stop-start sequence can be replaced by a repeated start (sr). fig 18. master reads after setting register address (write register address; read data) % 3%333%% $6#*, &2 9 *!.130 $5 *"#6 ! # ! !* > 2"( $&& (( $5 *"#6 ! # ! !* > 2"( $&& (( $6#*, &2 9 *!!$( ($+ $&& (( $&<" 3 *#&$ $<> ( #*$6#*, &2 % 3 % 3 3 3 % 3 $6#*, &2 9 *!.130 $6#*, &2 9 *!.130 ( 2"( $&& (( $& 2"( &$ $ ($+ $&& (( , " <" 2"( $&& (( 334 *3 4 PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 26 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 10. internal circuitry 11. limiting values [1] pass level; human body model (hbm) according to ref. 7 ? jesd22-a114 ? . [2] pass level; charged-device model (cdm), according to ref. 8 ? jesd22-c101 ? . [3] pass level; latch-up testing, according to ref. 9 ? jesd78 ? at maximum ambient temperature (t amb(max) ). [4] according to the store and transport requirements (see ref. 13 ? um10569 ? ) the devices have to be stored at a temperature of +8 ? c to +45 ? c and a humidity of 25 % to 75 %. fig 19. device diode protection diagram of PCF85063TP table 30. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.5 +6.5 v i dd supply current ? 50 +50 ma v i input voltage on pins scl, sda, osci ? 0.5 +6.5 v v o output voltage ? 0.5 +6.5 v i i input current at any input ? 10 +10 ma i o output current at any output ? 10 +10 ma p tot total power dissipation - 300 mw v esd electrostatic discharge voltage hbm [1] - ? 5000 v cdm [2] - ? 1500 v i lu latch-up current [3] -200ma t stg storage temperature [4] ? 65 +150 ?c t amb ambient temperature operating device ? 40 +85 ?c PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 27 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 12. characteristics table 31. static characteristics v dd = 0.9 v to 5.5 v; v ss =0v; t amb = ? 40 ? c to +85 ? c; f osc = 32.768 khz; quartz r s =60k ? ; c l = 7 pf; unless otherwise specified. symbol parameter conditions min typ max unit supplies v dd supply voltage interface inactive; f scl =0hz [1] 0.9- 5.5v interface active; f scl = 400 khz [1] 1.8- 5.5v i dd supply current v dd =3.3v [2] interface inactive; f scl =0hz t amb =25 ?c - 220 450 na t amb =50 ?c [3] - 250 500 na t amb =85 ?c - 470 600 na interface active; f scl = 400 khz -1850 ? a inputs [4] v i input voltage v ss -5 . 5v v il low-level input voltage v ss -0 . 3 v dd v v ih high-level input voltage 0.7v dd -v dd v i li input leakage current v i = v ss or v dd -0- ? a post esd event ? 0.15 - +0.15 ? a c i input capacitance [5] --7p f outputs v oh high-level output voltage on pin clkout 0.8v dd -v dd v v ol low-level output voltage on pins sda, int , clkout v ss -0 . 2 v dd v i oh high-level output current output source current; v oh = 2.9 v; v dd = 3.3 v; on pin clkout 13- ma i ol low-level output current output sink current; v ol =0.4v; v dd =3.3v on pin sda 3 8.5 - ma on pin int 26- ma on pin clkout 1 3 - ma PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 28 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar [1] for reliable oscillator start-up at power-on: v dd(po)min =v dd(min) +0.3v. [2] timer source clock = 1 60 hz, level of pins scl and sda is v dd or v ss . [3] tested on sample basis. [4] the i 2 c-bus interface of PCF85063TP is 5 v tolerant. [5] implicit by design. [6] integrated load capacitance, c l(itg) , is a calculation of c osci and c osco in series: . oscillator ? f osc /f osc relative oscilla tor frequency variation ? v dd =200mv; t amb =25 ?c - 0.075 - ppm c l(itg) integrated load capacitance on pins osco, osci [6] c l = 7 pf 4.2 7 9.8 pf c l = 12.5 pf 7.5 12.5 17.5 pf r s series resistance - - 100 k ? table 31. static characteristics ?continued v dd = 0.9 v to 5.5 v; v ss =0v; t amb = ? ? ? ? symbol parameter conditions min typ max unit c litg ?? c osci c osco ? ?? c osci c osco + ?? ------------------------------------------- - = t amb =25 ? c; clkout disabled. (1) v dd =5.0v. (2) v dd =3.3v. fig 20. typical i dd with respect to f scl 3 %33 33 33 -33 133 3 %3 3 3 -3 13 9 bc b: c b: c b: c b%c bc PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 29 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar c l(itg) = 7 pf; clkout disabled. (1) v dd =5.5v. (2) v dd =3.3v. c l(itg) = 12.5 pf; clkout disabled. (1) v dd =5.5v. (2) v dd =3.3v. fig 21. typical i dd as a function of temperature 13 3 %3 %3 3 13 /3 83 3 33 -33 033 .33 !) $ 5 bgc b# c b# c b# c b%c bc 13 3 %3 %3 3 13 /3 83 3 33 -33 033 .33 %333 !) $ 5 bgc b# c b# c b# c b%c bc PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 30 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar t amb =25 ? c; f clkout = 32768 hz. (1) 47 pf clkout load. (2) 22 pf clkout load. t amb =25 ? c; clkout disabled. (1) c l(itg) = 12.5 pf. (2) c l(itg) =7pf. fig 22. typical i dd with respect to v dd 3 % - 1 0 3 - 0 . %3 % b c b: c b: c b: c b%c b%c b%c bc bc bc 3 % - 1 0 3 %33 33 33 -33 133 b c b# c b# c b# c b%c bc PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 31 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar v dd = 3.3 v; clkout disabled. (1) c l(itg) = 12.5 pf; 50 ? c; maximum value. (2) c l(itg) =7pf; 50 ? c; maximum value. (3) c l(itg) = 12.5 pf; 25 ? c; typical value. (4) c l(itg) =7pf; 25 ? c; typical value. fig 23. i dd with respect to quartz r s t amb =25 ? c. (1) c l(itg) =7pf. (2) c l(itg) = 12.5 pf. fig 24. oscillator frequency variation with respect to v dd 3 3 -3 13 03 /3 .3 83 %33 3 33 -33 033 .33 bhc b# c b# c b# c b-c b-c b-c bc bc bc bc bc bc b%c b%c b%c 3 % - 1 0 %71 3 %71 b c i9 i9 *(6 *(6 i9 *(6 b))!c b))!c b))!c b%c bc PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 32 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar [1] a detailed description of the i 2 c-bus specification is given in ref. 12 ? um10204 ? . [2] i 2 c-bus access time between two starts or between a start and a stop condition to this device must be less than one second. table 32. i 2 c-bus characteristics v dd = 1.8 v to 5.5 v; v ss =0v; t amb = ? 40 ? c to +85 ? c; f osc = 32.768 khz; quartz r s =60k ? ; c l = 7 pf; unless otherwise specified. all timing values are valid within the operat ing supply voltage and temperature range and referenced to v il and v ih with an input voltage swing of v ss to v dd [1] . symbol parameter conditions min typ max unit c b capacitive load for each bus line - - 400 pf f scl scl clock frequency [2] 0- 400khz t hd;sta hold time (repeated) start condition 0.6 - - ? s t su;sta set-up time for a repeated start condition 0.6 - - ? s t low low period of the scl clock 1.3 - - ? s t high high period of the scl clock 0.6 - - ? s t r rise time of both sda and scl signals 20 + 0.1c b -0 . 3 ? s t f fall time of both sda and scl signals 20 + 0.1c b -0 . 3 ? s t buf bus free time between a stop and start condition 1.3 - - ? s t su;dat data set-up time 100 - - ns t hd;dat data hold time 0 - - ns t su;sto set-up time for stop condition 0.6 - - ? s t vd;dat data valid time 0 - 0.9 ? s t vd;ack data valid acknowledge time 0 - 0.9 ? s t sp pulse width of spikes that must be suppressed by the input filter 0- 50ns fig 25. i 2 c-bus timing diagram; rise and fall times refer to 30 % and 70 % scl sda t hd;sta t su;dat t hd;dat t f t buf t su;sta t low t high t vd;ack 013aaa417 t su;sto protocol start condition (s) bit 7 msb (a7) bit 6 (a6) bit 0 (r/w) acknowledge (a) stop condition (p) 1 /f scl t r t vd;dat PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 33 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 13. application information a 1 farad super capacitor combined with a low v f diode can be used as a standby or back-up supply. with the rtc in its minimum power conf iguration i.e. timer off and clkout off, the rtc may operate for weeks. fig 26. application diagram for PCF85063TP ; b <5(c % %33# ?)55) ( "( * @ < PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 34 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 14. package outline fig 27. package outline sot1069-2 (hwson8) of PCF85063TP references outline version european projection issue date iec jedec jeita sot1069-2 - - - mo-229 - - - sot1069-2_po 09-11-18 12-04-18 unit mm max nom min 0.80 0.75 0.70 0.05 0.02 0.00 2.1 2.0 1.9 1.6 1.5 1.4 3.1 3.0 2.9 0.5 1.5 0.45 0.40 0.35 0.05 a (1) dimensions note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. hwson8: plastic thermal enhanced very very thin small outline package; no leads; 8 terminals; body 2 x 3 x 0.75 mm sot1069-2 a 1 0.65 0.55 0.45 a 2 0.2 a 3 b 0.30 0.25 0.18 d (1) d 2 e (1) e 2 1.6 1.5 1.4 ee 1 k 0.40 0.35 0.30 lv 0.1 w 0.05 y 0.05 y 1 0 1 2 mm scale x c y c y 1 terminal 1 index area b a d e detail x a a 3 a 1 a 2 terminal 1 index area b e 1 e ac b v c w e 2 l k d 2 1 4 5 8 PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 35 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 15. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling metal-oxide semiconductor (mos) devices ensure that all normal precautions are taken as described in jesd625-a , iec 61340-5 or equivalent standards. 16. packing information 16.1 tape and reel information fig 28. tape and reel details for PCF85063TP table 33. carrier tape dimensions of PCF85063TP nominal values without production tolerances. symbol description value unit compartments a0 pocket width in x direction 2.25 mm b0 pocket width in y direction 3.25 mm k0 pocket depth 1.05 mm p1 pocket hole pitch 4 mm d1 pocket hole diameter 1 mm overall dimensions w tape width 8 mm d0 sprocket hole diameter 1.55 mm p0 sprocket hole pitch 4 mm &" 6 "*#*99 & 3 3 % 3 3 j 3 j % "2"#$&"! #("*#($ "#!!7 "25 #* & $,# *(6$ 7 )"#% PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 36 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 17. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 17.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 17.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 17.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 37 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 17.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 29 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 3 4 and 35 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 29 . table 34. snpb eutectic process (from j-std-020d) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 35. lead-free process (from j-std-020d) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 38 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . msl: moisture sensitivity level fig 29. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 39 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 18. footprint information fig 30. footprint information for reflow soldering of sot1069-2 (hwson8) of PCF85063TP %308 "#!! ** ) "# "#9* !$ "*#9* 9*,(*& "#2*9 .)$6$2 > > ' > ' > k' k> 7-1 7 371 371 3701 %70 %70 370 370 71 71 > 7/ #' # > %% *665)" &$ $ (*& $#&)5((*& )$( (*& $#& (*& )$( & )*(" (* %308e 9 ((5 &$ %338 %3 ' > >> k' k> > ' > #' #> PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 40 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 19. abbreviations table 36. abbreviations acronym description bcd binary coded decimal cmos complementary metal oxide semiconductor esd electrostatic discharge hbm human body model i 2 c inter-integrated circuit ic integrated circuit lsb least significant bit msb most significant bit msl moisture sensitivity level pcb printed-circuit board por power-on reset rtc real-time clock scl serial clock line sda serial data line smd surface mount device PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 41 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 20. references [1] an10365 ? surface mount reflow soldering description [2] an10366 ? hvqfn application information [3] an11247 ? improved timekeeping accuracy with pcf85063, pcf8523 and pcf2123 using an external temperature sensor [4] iec 60134 ? rating systems for electronic tu bes and valves and analogous semiconductor devices [5] iec 61340-5 ? protection of electronic devices from electrostatic phenomena [6] ipc/jedec j-std-020 ? moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices [7] jesd22-a114 ? electrostatic discharge (esd) sensitivity testing human body model (hbm) [8] jesd22-c101 ? field-induced charged-device model test method for electrostatic-discharge-withstand thresh olds of microelectronic components [9] jesd78 ? ic latch-up test [10] jesd625-a ? requirements for handling elec trostatic-discharge-sensitive (esds) devices [11] snv-fa-01-02 ? marking formats integrated circuits [12] um10204 ? i 2 c-bus specification and user manual [13] um10569 ? store and transport requirements 21. revision history table 37. revision history document id release date data sheet status change notice supersedes PCF85063TP v.2 20130415 product data sheet - PCF85063TP v.1 modifications: ? improved description of correction pulses ( ta b l e 1 4 and table 16 ) ? adjusted i dd and i li values ( ta b l e 3 1 ) ? updated figure 19 PCF85063TP v.1 20130122 objective data sheet - - PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 42 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 22. legal information 22.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 22.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 22.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification. PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 43 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 22.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 23. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 44 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 24. tables table 1. ordering information . . . . . . . . . . . . . . . . . . . . .2 table 2. ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2 table 3. marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2 table 4. pin description . . . . . . . . . . . . . . . . . . . . . . . . . .3 table 5. registers overview . . . . . . . . . . . . . . . . . . . . . .5 table 6. control_1 - contro l and status register 1 (address 00h) bit description . . . . . . . . . . . . . . .6 table 7. first increment of time circuits after stop bit release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 table 8. register reset values . . . . . . . . . . . . . . . . . . . . .9 table 9. control_2 - contro l and status register 2 (address 01h) bit description . . . . . . . . . . . . . .10 table 10. effect of bits mi and hmi on int generation . .10 table 11. clkout frequency selection . . . . . . . . . . . . . 11 table 12. offset - offset register (address 02h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 13. offset values . . . . . . . . . . . . . . . . . . . . . . . . . .12 table 14. correction pulses for mode = 0 . . . . . . . . . . .13 table 15. effect of correction pulses on frequencies for mode = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 table 16. correction pulses for mode = 1 . . . . . . . . . . .14 table 17. effect of correction pulses on frequencies for mode = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 table 18. ram_byte - 8-bit ram register (address 03h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 19. seconds - seconds register (address 04h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 table 20. seconds coded in bcd format . . . . . . . . . . . .17 table 21. minutes - minutes register (address 05h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 22. hours - hours register (address 06h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 23. days - days register (address 07h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 table 24. weekdays - weekdays register (address 08h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .18 table 25. weekday assignments . . . . . . . . . . . . . . . . . . .19 table 26. months - months register (address 09h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 table 27. month assignments in bcd format . . . . . . . . . .19 table 28. years - years register (0ah) bit description. . . .20 table 29. i 2 c slave address byte . . . . . . . . . . . . . . . . . . .24 table 30. limiting values . . . . . . . . . . . . . . . . . . . . . . . . .26 table 31. static characteristics . . . . . . . . . . . . . . . . . . . .27 table 32. i 2 c-bus characteristics . . . . . . . . . . . . . . . . . . .32 table 33. carrier tape dimensions of PCF85063TP . . . .35 table 34. snpb eutectic process (from j-std-020d) . . .37 table 35. lead-free process (from j-std-020d) . . . . . .37 table 36. abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .40 table 37. revision history . . . . . . . . . . . . . . . . . . . . . . . .41 PCF85063TP all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 15 april 2013 45 of 46 nxp semiconductors PCF85063TP tiny real-time clock/calendar 25. figures fig 1. block diagram of PCF85063TP . . . . . . . . . . . . . . .2 fig 2. pin configuration fo r hwson8 (PCF85063TP) . . .3 fig 3. handling address registers . . . . . . . . . . . . . . . . . .4 fig 4. stop bit functional diagram . . . . . . . . . . . . . . . . .7 fig 5. stop bit release timing . . . . . . . . . . . . . . . . . . . . .8 fig 6. software reset command . . . . . . . . . . . . . . . . . . . .9 fig 7. int example for mi . . . . . . . . . . . . . . . . . . . . . . .10 fig 8. offset calibration calculation workflow . . . . . . . . .15 fig 9. result of offset calibration . . . . . . . . . . . . . . . . . .16 fig 10. os flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 fig 11. data flow for the time function . . . . . . . . . . . . . . .20 fig 12. access time for read/write operations . . . . . . . . .21 fig 13. bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 fig 14. definition of start and stop conditions. . . . . .22 fig 15. system configuration . . . . . . . . . . . . . . . . . . . . . .23 fig 16. acknowledgement on the i 2 c-bus . . . . . . . . . . . .23 fig 17. master transmits to slave receiver (write mode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 fig 18. master reads after setting register address (write register address; read data) . . . . . . . .25 fig 19. device diode protection diagram of PCF85063TP . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 fig 20. typical i dd with respect to f scl . . . . . . . . . . . . . .28 fig 21. typical i dd as a function of temperature . . . . . . .29 fig 22. typical i dd with respect to v dd . . . . . . . . . . . . . .30 fig 23. i dd with respect to quartz r s . . . . . . . . . . . . . . . .31 fig 24. oscillator frequency variation with respect to v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 fig 25. i 2 c-bus timing diagram; rise and fall times refer to 30 % and 70 % . . . . . . . . . . . . . . . . . . . . . . . .32 fig 26. application diagram for PCF85063TP . . . . . . . . .33 fig 27. package outline sot1069-2 (hwson8) of PCF85063TP . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 fig 28. tape and reel details for PCF85063TP . . . . . . . .35 fig 29. temperature profiles for large and small components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 fig 30. footprint information for reflow soldering of sot1069-2 (hwson8) of PCF85063TP . . . . . .39 nxp semiconductors PCF85063TP tiny real-time clock/calendar ? nxp b.v. 2013. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 15 april 2013 document identifier: PCF85063TP please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 26. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 8 functional description . . . . . . . . . . . . . . . . . . . 4 8.1 registers organization . . . . . . . . . . . . . . . . . . . 5 8.2 control registers . . . . . . . . . . . . . . . . . . . . . . . . 6 8.2.1 register control_1 . . . . . . . . . . . . . . . . . . . . . . 6 8.2.1.1 ext_test: external clock test mode . . . . . . . . 6 8.2.1.2 stop: stop bit function . . . . . . . . . . . . . . . . . 7 8.2.1.3 software reset. . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.2.2 register control_2 . . . . . . . . . . . . . . . . . . . . . 10 8.2.2.1 mi and hmi: minute and half minute interrupt. 10 8.2.2.2 tf: timer flag . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.2.2.3 cof[2:0]: clo ck output frequency . . . . . . . . . 11 8.2.3 register offset . . . . . . . . . . . . . . . . . . . . . . . . 11 8.2.3.1 correction when mode = 0 . . . . . . . . . . . . . . 13 8.2.3.2 correction when mode = 1 . . . . . . . . . . . . . . 14 8.2.3.3 offset calibration workflow . . . . . . . . . . . . . . . 15 8.2.4 register ram_byte . . . . . . . . . . . . . . . . . . . . 16 8.3 time and date registers . . . . . . . . . . . . . . . . . 16 8.3.1 register seconds . . . . . . . . . . . . . . . . . . . . . . 16 8.3.1.1 os: oscillator stop . . . . . . . . . . . . . . . . . . . . . 17 8.3.2 register minutes. . . . . . . . . . . . . . . . . . . . . . . 18 8.3.3 register hours . . . . . . . . . . . . . . . . . . . . . . . . 18 8.3.4 register days . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.3.5 register weekdays. . . . . . . . . . . . . . . . . . . . . 18 8.3.6 register months . . . . . . . . . . . . . . . . . . . . . . . 19 8.3.7 register years . . . . . . . . . . . . . . . . . . . . . . . . 20 8.4 setting and reading the time. . . . . . . . . . . . . . 20 9 characteristics of the i 2 c-bus interface . . . . 22 9.1 bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 9.2 start and stop conditions . . . . . . . . . . . . . 22 9.3 system configuration . . . . . . . . . . . . . . . . . . . 22 9.4 acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.5 i 2 c-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 24 9.5.1 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.5.2 clock and calendar read or write cycles . 24 10 internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 26 11 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 26 12 characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27 13 application information . . . . . . . . . . . . . . . . . 33 14 package outline. . . . . . . . . . . . . . . . . . . . . . . . 34 15 handling information . . . . . . . . . . . . . . . . . . . 35 16 packing information . . . . . . . . . . . . . . . . . . . . 35 16.1 tape and reel information . . . . . . . . . . . . . . . 35 17 soldering of smd packages . . . . . . . . . . . . . . 36 17.1 introduction to soldering. . . . . . . . . . . . . . . . . 36 17.2 wave and reflow soldering. . . . . . . . . . . . . . . 36 17.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . 36 17.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . 37 18 footprint information . . . . . . . . . . . . . . . . . . . 39 19 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 40 20 references. . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 21 revision history . . . . . . . . . . . . . . . . . . . . . . . 41 22 legal information . . . . . . . . . . . . . . . . . . . . . . 42 22.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 42 22.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 22.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 42 22.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 43 23 contact information . . . . . . . . . . . . . . . . . . . . 43 24 tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 25 figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 26 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 |
Price & Availability of PCF85063TP
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |